Error tends to happen at critical point.

Next Monday, Another IC will be tape out. So I work over time yesterday.

I found an interesting thing that errors tend to happen in the key point.  We have done many times without any problems before. But when it comes to be taped out, error occurred.

I must think it over and over to strengthen our design flow. How to prevent it to happen again?

We must improve our flow.  All the time we must do it.